As is well-known to those skilled in the art, integrated circuit memory devices include random access memory (RAM) devices, which generally do not retain stored information when power is interrupted, and read only memory (ROM) devices, which generally retain their stored information despite power failure. For this reason, the latter devices art often referred to as nonvolatile memory devices. Nonvolatile memory devices include "flash" electrically-erasable programmable read only memory (EEPROM) devices, which may be electrically erased and programmed. Flash EEPROMs are widely used for computers, memory cards, and the like.
Conventional flash EEPROMs may utilize various kinds of memory cells. The conventional cell structures used include simple stack-gate cells, as described in Tam et al., "A High Density CMOS 1-T Electrically Eraseable Non-Volatile (Flash) Memory Technology," VLSI Technology, 1988, IV-4, pp. 31-32. A stack-gate cell typically includes a transistor having source and drain regions, and a gate including a floating gate electrode and control gate electrode, with the floating gate serving to store data and the control gate serving to control the data stored by the floating gate. Typically, an erase operation lowers the threshold voltage of the stack-gate cell by tunneling electrons from the floating gate electrode to the source and drain regions, while a program operation increases the threshold voltage of the cell by injecting hot electrons generated in a channel region between the source and drain regions into the floating gate electrode using potentials at the gate electrode and drain regions that are higher than a potential supplied to the source region. A read operation reads the state of the cell.
The simple stack-gate cell has several disadvantages in its structure and operations. As programming is typically performed by hot electron injection, the cycling endurance of the erase/program operations may be sharply lowered, which may degrade cell performance. Non-selected cells may be disturbed during program or read operations, and cells may become over-erased, i.e., may be put into a state in which they have a threshold voltage lower than 0 V.
Stacked-gate cells typically have structural features which may complicate fabrication. Although only one single transistor may be used for each cell, a bit line may be required for every two cells. Also, since the source regions of cells typically are commonly connected in an active region, a corner rounding phenomenon may occur during oxidation to form a field oxide layer, thereby increasing the threshold voltage dissipation of the cell after erase and program operations.
A DINOR (DIvided bit line NOR) cell has been proposed to avoid some of the problems associated with the stack-gate cell, as described Kobayashi et al., "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Eraseable DINOR Flash Memory," VLSI Circuits, 1993, pp. 97-98. FIGS. 1 and 2 are a schematic diagram and a cross-sectional view of a conventional flash EEPROM utilizing a DINOR cell, respectively. The DINOR cell includes word lines WL1 through WLi for selecting a desired cell transistor, a select transistor line 3 having select transistors 3a, main bit lines 1 connected to the drain of a select transistor 3a, and sub bit lines 5 connected to the source of the select transistor 3a, typically formed as a polysilicon layer. A DINOR cell typically has a string-like structure wherein adjacent cell transistors are connected in parallel through the sub bit lines 5 connected to the drains of the transistors and source line 7 connected to the sources of the adjacent transistors. As illustrated in FIG. 1, a unit block A includes a select transistor 3a, eight memory cells, and one sub bit line 5 connected to main bit line 1 through the select transistor 3a.
To erase a cell, approximately 10 V is applied to a word line W/L1, and approximately 8 V is applied to source line 7 and the p-well or substrate upon which the cell is formed, thereby causing tunneling of electrons from the well or substrate to the floating gate electrode and increasing the threshold voltage to approximately 6-7 V. Programming may be achieved by applying a negative voltage of about -8 V to the word line W/L1 and applying approximately 5 V to a bit line 1, thereby tunneling electrons from the floating gate electrode to the drain of the cell and decreasing the threshold voltage. Fabrication of DINOR cells typically is complex, involving a large number of process steps. Typically, a self-aligned source, a self-aligned bitline contact and a tungsten plug must be fabricated in addition to the basic structures of the stack-gate cell. In forming the self-aligned bit line contact and sub bit lines, a stringer may be generated, thus reducing yields. Also, during etching of a thick field oxide layer to form the self-aligned source, the surface of the silicon substrate may be damaged, thereby degrading the cell characteristics due to leakage current. In addition, as the sources of cells are commonly connected in the direction of adjacent word lines, the resistance of the source line generally is increased and an extra circuit for decoding the source may be necessary, complicating the design and increasing the size of the row decoder.
An AND cell has been proposed as an alternative to the stack-gate cell, as described in IEDM, pp. 991-993, 1992 and IEDM, pp. 921-923, 1994. As illustrated in FIG. 3, a unit block B includes a plurality of memory cells connected in parallel, a local data line 11 for connecting the drains of the memory cells, a local source line 13 for connecting the sources of the memory cells, data and source select transistors ST1, ST2 for selecting the local data lines 11 and the local source lines 13, global data lines 15 (D0-Dn) connected to the data select transistors ST1, and a common source line 17 connected to the source select transistor ST2.
To erase a cell, approximately 0 V is applied to the source and drain of the cell, as well as to the well or substrate upon which the cell is formed. Approximately 13 V is applied to the associated word line, thereby tunneling electrons from the well or substrate to the floating gate electrode and increasing the threshold voltage of the cell to approximately 6-7 V. Programming is achieved by applying a voltage of approximately -9 V to the word line and applying approximately 3 V to the drain of the cell, thereby tunneling electrons from the floating gate to the drain and decreasing the threshold voltage of the cell to approximately 1-2 V.
The local source line 13 and local data line 11 typically are doped n.sup.+ -diffusion layers. This may simplify fabrication in comparison to a DINOR structure, in that the space and processes used for forming bit lines may be eliminated. As illustrated in FIGS. 4A-4B, the floating gate 19 typically is composed of a double stack of polysilicon layers, underlying word line 19 and insulation layer 21. Isolation between channels of the cell is achieved by using a self-aligned junction layer 25 formed by ion implantation. The parallel structure in the direction of the global data lines 15 can help increase density, but two source/drain regions 23a, 23b, typically diffusion layers, as well as a field insulation layer 27 typically lie between adjacent floating gate electrodes 16. This may limit the density which may be achieved, as reducing the size of the source/drain regions 23a, 23b tends to increase resistance and degrade cell performance.